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Caller ID Detector (Japan) TMS320C5000 DSP Code

Description: implements Caller IDentity - CID - detection for communicating call data on-hook over telephone lines to subscribers as implemented in Japan. Here before the 1st normal ring, the exchange sends a line reversal followed by a set of short rings that should be inaudible in a normal subscriber phone. The phone responds by going off-hook, triggering the exchange to send the CID message data. After reception, the phone reverts to on-hook, and the exchange continues with normal ringing.
         The CID message is a pre-amble of mark carrier followed by the message byte data and finally a cyclic redundancy check (CRC) byte-pair, all modulated as a V.23 modem signal. The byte data consists of multiple parameter groups. The CID Detector - Decoder+Receiver - implements the message data communication for the subscriber end. The software function summary is:

CID Decoder - accepts the pre-amble of mark carrier signal for a user-set minimum period, followed by the fixed start 5 bytes, then loads received bytes into the message data buffer stripping parity, then the fixed end 2 bytes, and finally checks the received CRC byte-pair

The function above detects from line signal samples using the following routine, available on its own:

CID Receiver (as used with "standard" CID) - with timing at 1200b/s, frequency-demodulates V.23 (1300Hz Mark, 2100Hz Space) receive samples to pre-amble data or message data bytes, stripping out start/stop bits

The Detector forms a buffer of the complete message data for the user interface in parameterised byte form, excluding the CRC bytes. Message de-parameterisation in the user code gives flexibility in dealing with Caller ID categories. The message buffer format is 2 per 16-bit word for efficiency in multi-channel use.
         Each function has an initialisation routine and a per-sample main routine and is re-entrant with memory offset-addressing for multi-channel operation. As well as from assembler, the routines can also be called from C, wrappers being provided. The C main routines enable multiple sample blocks to be processed. Sample rates of 8.0kHz or 9.6kHz can be set. A comprehensive user's guide is provided with the code.

Performance:

Processor Load:

- #figures are for TMS320C54x operation with the assembler interface at 8.0kHz sampling
- in data memory figures M is the user-set buffer size at 2 bytes per word and N is no. of channels

Availability: NOW - sale is under licence - integration support offered